1. Field of the Invention
The present invention relates to a semiconductor memory device and manufacturing method thereof and, more specifically, to a DRAM (Dynamic Random Access Memory) having a stacked type capacitor as a capacitive element of a memory cell and to a manufacturing method thereof.
2. Description of the Background Art
Thanks to development in semiconductor technology, especially in microprocessing technique, degree of integration and capacity of DRAMs have ever been improved.
As the degree of integration becomes higher and the capacity is increased, the area occupied by a capacitive element (capacitor) for storing information (charges) decreases. As a result, erroneous reading of the stored memory content, or soft error caused by destruction of stored content by an .alpha. line becomes more likely. In order to solve such a problem by increasing substantial area of the capacitive element, a stacked capacitor type memory cell, in which a storage node serving as one electrode and a cell plate serving as another electrode of the capacitive element are formed on one major surface of a semiconductor substrate has been proposed.
FIGS. 19 to 21 show a conventional typical DRAM having a stacked type capacitor. Each of a plurality of memory cells formed on one major surface of a semiconductor substrate 1 includes one transistor element (a transfer gate transistor formed by an MOS transistor) and one capacitive element (a capacitor including a storage node and a cell plate).
The transistor element of each memory cell consists of a pair of source/drain regions 3 and 4 and a gate electrode. The pair of source/drain regions 3 and 4 are formed in an element forming region (active region) of a major surface of semiconductor substrate 1 surrounded by an element isolating insulating film 2 formed on one major surface of semiconductor substrate 1. The gate electrode is formed on a channel sandwiched by the pair of source/drain regions with a gate oxide film interposed, and it is formed of a part of a corresponding word line 5.
Word lines 5 are arranged parallel to each other. Each word line 5 is electrically connected to a corresponding plurality of memory cells, that is, gate electrodes of transistor elements of the memory cells provided in the same row, in other words, it is formed physically integrated.
The capacitive element of each memory cell includes a storage node 6, and a cell plate 7 placed opposite to the surface of storage node 6 with a dielectric film 8 interposed. Storage node 6 is electrically connected to the other one of the source.cndot.drain regions 4 of the corresponding transistor element, and extending to an adjacent word line positioned on the element isolating insulating film from the gate electrode of the corresponding transistor element.
Cell plate 7 has an opening 7a on one of the source/drain regions 3 of the transistor element of the memory cell, and has a flat shape.
Bit lines 9 are arranged orthogonal to word lines 5 and parallel to each other. Each bit line 9 is electrically connected to the corresponding plurality of memory cells, that is, to one of the source/drain regions 3 of the transistor element of the memory cells provided in the same column, and formed on the cell plate with interlayer insulating layer 10 interposed.
An interlayer insulating layer 11 is formed on the bit line.
The feature of the DRAM structured as described above is that though two-dimensional area of occupation of each memory cell is small, opposing area of electrodes of the capacitive element is increased so as to ensure increased capacitance value, as the capacitive element of the memory cell is formed extending over the gate electrode of the corresponding transistor element and to the adjacent word line.
Meanwhile, since the element becomes smaller and smaller as the degree of integration becomes higher, increase of the capacitance value by arranging the storage node constituting the capacitive element of the memory cell over the bit line to increase the opposing area of electrodes of the capacitive element has been proposed (for example, see 1990 Symposium on VLSI Technology P. 13 or Japanese Patent Laying-Open No. 5-29579).
FIGS. 22 to 26 show a DRAM proposed based on such concept.
Each of the plurality of memory cells formed on one major surface of a semiconductor substrate 100 includes one transistor element (a transfer gate transistor consisting of an MOS transistor) and one capacitive element (a capacitor consisting of a storage node and a cell plate).
The transistor element of each memory cell includes a pair of source/drain regions 103 and 104, and a gate electrode. The pair of source/drain regions 103 and 104 are formed in an element forming region (active region) 102 (shown surrounded by one dotted line and formed obliquely in FIG. 22) on one major surface of semiconductor substrate 100, surrounded by an element isolating insulating film 101 formed on the major surface of semiconductor substrate 100. The gate electrode is formed by a part of a corresponding word line 107 which is formed on a channel 105 sandwiched by the pair of source/drain regions 103 and 104 with a gate oxide film 106 interposed.
Each word line 107 is formed by a first conductive layer on the major surface of semiconductor substrate 100 and arranged parallel to each other. Each word line 107 is electrically connected to, that is, physically integrated with, the corresponding plurality of memory cells, or the gate electrodes of transistor elements of the memory cells provided on the same row in the circuit structure.
Each bit line 108 is formed by a second conductive layer positioned above the first conductive layer forming the word line 107, on the major surface of semiconductor substrate 100. Bit lines 108 are arranged parallel to each other and orthogonal to the word lines 107. Further, each bit line 108 is electrically connected to the corresponding plurality of memory cells, that is, one of the source/drain regions 103 of the transistor elements of the memory cells provided on the same column in the circuit structure, and formed above the word line 107 with an interlayer insulating layer 109 interposed therebetween.
The capacitive element of each memory cell consists of a storage node 110 electrically connected to the other one of the source/drain regions 104 of the corresponding transistor element, and a cell plate 111 formed on and opposing to the surface of storage node 110 with a dielectric film 112 interposed.
Each storage node 110 is formed by a third conductive layer positioned above the second conductive layer forming the bit line 108, on one major surface of semiconductor substrate 100, with an interlayer insulating layer 113 interposed. Further, each storage node 110 is electrically connected to the other one of the source/drain regions 104 of the corresponding memory cell. Further, the storage node 110 is positioned between a bit line to which the corresponding memory cell is connected, and an adjacent bit line on the side of the other one of the source/drain regions 104 of the transistor element of the corresponding memory cell with respect to said bit line, and crossing the word line to which the corresponding memory cell is connected.
The cell plate 111 is formed to have a flat shape.
Referring to FIG. 22, a bit line contact 114 (denoted by a black circle) indicates an electrical connection between one of the source/drain regions 103 of the transistor element of the memory cell and bit line 108. A storage node contact 115 (denoted by a white circle) indicates an electrical contact with one of the source/drain regions 104 of the transistor element of the memory cell and the storage node 110 of the capacitive element of the memory cell.
Referring to FIG. 22, a portion (denoted by a reference numeral 116) around storage node 110 which is painted black indicates are "dimension loss" which is the difference between the design of storage node 110 and the actual finish, that is, the lost portion. The outer periphery of dimension loss 116 represents the design of storage node 110, and the inner periphery represents the outer periphery of the actually finished storage node 110.
In the DRAM structured as described above, storage node 110 of the capacitive element of the memory cell is formed by the layer above the bit line 108, and therefore large opposing area of storage node 110 and cell plate 111 can be ensured, thus large capacitance value is obtained. However, if the arrangement pitch of word line 107 is made approximately equal to the pitch of bit lines 108 in order to realize highest density of memory cells, the following problem arises.
More specifically, since storage node 110 is formed in a depressed portion between two adjacent bit lines 108, the longer side of storage node 110 is positioned on the inclined surface of interlayer insulating layer 113. Accordingly, at the time of exposure for forming a resist pattern to form storage node 110, the light reflected from the inclined surface of interlayer insulating layer 113 exposes portions inner than the design as shown in FIGS. 27 to 29, and thus the resist pattern becomes thinner. As a result, in the actual finish of storage node 110, there is the dimension loss from the design at the longer side portion.
Therefore, the capacitance value of the capacitive elements obtained is smaller than the design, which results in degradation in characteristics of the DRAM such as hold time of the stored charges in the capacitive element, and further leads to degradation in soft error characteristic.
FIG. 27 shows exposure for forming a resist pattern for storage node 110. More specifically, on the entire surface of interlayer insulating layer 113 on bit line 108, a third conductive layer 110a for forming the storage node 110 is provided. Resist 117a is applied to the third conductive layer 110a. FIG. 27 shows irradiation of resist 117a with light, using a storage node mask 118. Storage node mask 118 includes a light intercepting portion 118a which does not pass the light for forming storage node 110, and light transmitting portion 118b. Resist 117a is a positive photoresist. Hatched portion in resist 117a denotes a portion exposed by the light which has passed through the light transmitting portion 118b of mask 118. Cross hatched portion of resist 117a denotes a portion exposed by the light 119a reflected from the inclined surface of interlayer insulating layer 113 resulting from bit line 108.
FIG. 28 shows resist pattern 117 formed by development of resist 117a. Portions exposed by the light which has passed through light transmitting portion 118b of mask 118 and light 119a reflected from the inclined surface of interlayer insulating layer 113 are removed. Resist 117 left for forming storage node 110 is thinner than the width of the light intercepting portion 118a of mask 118.
FIG. 29 shows a state in which storage node 110 is formed by etching the third conductive layer 110a based on resist pattern 117. The width of storage node is approximately the same as that of resist pattern 117. However, the width of resist pattern 117 is thinner than that of light intercepting portion 118a of mask 118.
In the actual finish, there is a dimension loss in the shorter side portion of storage node 110 from the design. This is because there is strong diffraction effect of light at end portions of the shorter side of the rectangle, when resist pattern 117 is obtained from resist 117a.
Referring to FIG. 30, description will be given as to how much dimension loss results in the actual finishing of storage node 110 from the design.
The example shown in FIG. 30 is designed with the design rule of 0.25 .mu.m, the width between word lines 107 and bit lines 108 of 0.25 .mu.m, the width of word line 107 and bit line 108 of 0.25 .mu.m, base pitch (space between word lines 107 and space between bit lines 108) of 0.6 .mu.m, and the design of storage node 110 of 0.35 .mu.m (shorter side).times.0.95 .mu.m (longer side).
In this example, the reduction x of the longer side of storage node 110 is not smaller than 0.02-0.05 .mu.m (x.gtoreq.0.02 to 0.05 .mu.m), and the area of the dimension loss 116 was at least 20% with respect to the area of the design.
In the DRAM structured as described above, in order to prevent dimension loss at the longer side portion of storage node 110, in other words, in order to prevent influence of the light 119a reflected from the inclined surface of interlayer insulating layer 113 on the longer side portion of storage node 110, the longer side of storage node 110 may be designed to rest against bit line 108.
However, if it is designed with the design rule of 0.25 .mu.m, the space of resist pattern 117 positioned between longer sides of adjacent storage node 110 becomes narrower than the width of the bit line. Therefore, at the time of development, resists 117a positioned between longer sides of adjacent storage node 110 are not resolved but connected. As a result, there arises a problem that longer sides of adjacent storage nodes 110 are connected.